This vertical transistor on which IBM and Samsung are betting to push the limits of Moore's law

From horizontal to vertical

On December 14, 2021, IBM and Samsung made a switchover. The two manufacturers presented their new transistor architecture. Called VTFET, for “Vertical transport field effect transistor”, it is made up of the same elements as a conventional transistor, but assembled vertically. The current flows between the source and the drain, positioned one above the other and no longer one next to the other. Between the two is the conduction channel where the electrons circulate, surrounded by the grid. This ensures the electrostatic control of the opening of the channel. “The VTFET transistors will allow miniaturization to continue after the GAA nanosheet transistors, indicates Huiming Bu, vice-president at IBM Research. These will be used for two or three generations of chips. Not yet commercialized, GAA transistors will be at the heart of the 3 nanometer (nm) and 2 nm technologies that Samsung plans to produce in 2022 and 2025 respectively. Intel will use them for its 2 nm chips in 2024. Huiming Bu imagines that the GAA nanosheet technology will still be used for the 1.5nm technology node (which could also be called 1.4nm). It should be noted that today, the most advanced technological node on the market is the 5 nm based on FinFET, by Samsung and TSMC.

The end of the technological node

With their VTFET transistor, IBM and Samsung are shelving this notion of a technological node. If this quantity used to designate the distance between the source and the drain, it has not corresponded to any physical quantity for years, since the architectures of transistors have become more complex. To quantify the increase in the density of transistors per chip, the two manufacturers opt for the “contacted gate pitch” (CGP). It corresponds to the minimum distance between the conduction channels of two neighboring transistors. The VTFET should make it possible to achieve less than 40 nm, estimates IBM. For comparison, for 22 nm to 3 nm technology nodes based on FinFET, the CGP is between 90 and 48 nm. For technology nodes below 3 nm, nanosheet GAA transistors will achieve CGP between 50 and 40 nm.

Nearly 100 billion transistors on 1 cm2

VTFET is expected to double circuit performance or reduce power consumption by 85% compared to current FinFET technology, says IBM. “We should be able to integrate between 80 and 100 billion transistors on a surface which today accommodates 10 to 20 billion FinFETs”, assures Huiming Bu. This is twice as many as the 30 to 50 billion nanosheet GAA transistors that can be envisaged on the same surface of approximately one square centimeter. Enough to meet the needs of applications where the challenges of energy, miniaturization and performance are the highest. Like high performance computing or mobile devices. If IBM indicates that it has been working on VTFETs for a little over 6 years, Huiming Bu does not imagine an industrialization of these transistors before 6 to 8 years. That is a period of about 12 to 14 years between the start of the work and industrialization. The same one that the FinFETs will have needed. And the same as the one that will be needed for the nanosheet GAAs on which IBM says it has been working for more than 12 years.

Different manufacturing process

While the manufacturing process for GAA nanosheet transistors is very similar to that of FinFETs, a lot of things change with VTFET, assures Hemanth Jagannathan, hardware technology researcher at IBM Research: “The source and the drain are no longer manufactured at the same time, for example. And metal contacts are not made the same. But the tools we need are not radically different. »